Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) or MOS transistors are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel. Some semiconductor ICs, such as high performance microprocessors, can include millions of FETs. For such ICs, decreasing transistor size and thus increasing transistor density has traditionally been a high priority in the semiconductor manufacturing industry. Transistor performance, however, must be maintained even as the transistor size decreases.
A FinFET is a type of transistor that lends itself to the goals of reducing transistor size while maintaining transistor performance. The FinFET is a non-planar, three dimensional transistor formed in and on a thin fin that extends upwardly from a semiconductor substrate. The semiconductor substrate may be a bulk silicon wafer from which the fins are formed or may be a silicon-on-insulator (SOI) wafer disposed on a support substrate. The SOI wafer includes a silicon oxide layer and a silicon-containing material layer overlying the silicon oxide layer. The fins are formed from the silicon-containing material layer. The fins are typically formed using conventional photolithographic or anisotropic etching processes (e.g., reactive ion etching (RIE) or the like).
The following brief explanation is provided to identify some of the unique features of FinFETs. FIG. 1 illustrates, in a cut away perspective view, a portion of a FinFET integrated circuit (IC) 10 known from the prior art. As illustrated, the IC 10 includes two fins 12 and 14 that are formed from and extend upwardly from a bulk semiconductor substrate 16. A gate electrode 18 overlies the two fins 12 and 14 and is electrically insulated from the fins 12 and 14 by a gate insulator (not illustrated). An end 20 of the fin 12 is appropriately impurity doped to form a source (not shown) of a FinFET 22, and an end 24 of the fin 12 is appropriately impurity doped to form a drain (not shown) of the FinFET 22. Similarly, the ends 26 and 28 of the fin 14 form the source and drain, respectively, of another FinFET 30.
The illustrated portion of IC 10 thus includes two FinFETs 22 and 30 having a common gate electrode 18. In another configuration, if the ends 20 and 26 that form the sources are electrically coupled together and the ends 24 and 28 that form the drains are electrically coupled together, the structure would be a two-fin FinFET having twice the gate width of either FinFET 22 or 30. An oxide layer 32 deposited onto the bulk semiconductor substrate 16 forms electrical isolation (e.g., shallow trench isolation (STI)) structures between the fins 12 and 14 and between adjacent devices as is needed for the circuit being implemented. The channel of the FinFET 22 extends along a sidewall 34 of the fin 12 beneath the gate electrode 18, along a top 36 of the fin 12, as well as along an opposite sidewall not visible in this perspective view. The advantage of the FinFET structure is that although the fin 12 has only a narrow width (indicated by the arrows 38), the channel has a width represented by at least twice the height of the fin 12 above the oxide layer 32. The channel width thus can be much greater than fin width.
The fins 12 and 14 are formed according to known processes. For instance, portions of the bulk semiconductor substrate 16 are etched or otherwise removed leaving the fins 12 and 14. The oxide layer 32 is formed by depositing and planarizing a dielectric material via FCVD and CMP processes, respectively, and partially etching the dielectric material to expose the upper portions of the fins 12 and 14. As noted above, it is the formation of this oxide layer using convention FCVD with high-temperature annealing that has caused some of process variabilities such as fin bending and insufficient oxide layer densification. The gate electrode 18 is then formed across the fins 12 and 14. Gate oxide insulator and/or nitride capping layers (not shown) may be deposited over the fins 12 and 14 before the gate electrode 18 is formed. The gate electrode 18 is formed by typical lithographic processing.
Electrical isolation of the fins is necessary to avoid electromechanical interference (EMI) and/or parasitic leakage paths between the various devices. Isolating fins on a bulk silicon wafer is especially problematic as the silicon of the bulk silicon wafer between the fins forms a conductive path. Shallow trench isolation (STI) is a technique used to electrically isolate transistors or electrical devices. Typically, STI structures are created during a relatively early fabrication stage(s), before the transistors are formed. A conventional STI process for FinFET devices involves creating isolation trenches in the semiconductor substrate through an anisotropic etch process. The isolation trench between each adjacent fin structures has a relatively high aspect ratio (e.g., ratio of the depth of the isolation trench to its width). A dielectric filler material, such as silicon oxide, is deposited into the isolation trenches to fill the isolation trenches. The deposited dielectric material may then be polished by a chemical-mechanical polishing (CMP) process that removes the excess dielectric material and creates a planar STI structure. The planarized oxide is etched back to form partially recessed uniformly thick oxide STI structures between the fin structures and to expose the upper vertical sidewalls of the fins for further processing.
As FinFET devices are designed at smaller and smaller scales, however, such as at the 14 nm regime, the 10 nm regime, and beyond, it becomes increasingly difficult to adequately and reliably form the STI structures in the isolation trenches. One solution proposed in the prior art is the use of flowable chemical vapor deposition (FCVD) techniques to fill the isolation trenches and form the STI structures. FCVD methods involve placing a substrate into a reaction chamber and introducing a vapor phase silicon-containing compound and an oxidant into the chamber. Reactor conditions are controlled so that the silicon-containing compound and the oxidant are made to react and condense onto the substrate. The chemical reaction causes the formation of a flowable film, for example including Si—OH, Si—H, and Si—O bonds. The flowable film reliably fills isolation trenches on the substrates. The flowable film is then converted into a final, solid silicon oxide film, for example by high-temperature plasma or thermal annealing.
While FCVD has been demonstrated to adequately and reliably fill high aspect ratio trenches for forming STI structures at increasingly smaller pitches, current FCVD processes, which use relatively high temperature plasma or thermal annealing (i.e., about 600° C. or greater), introduce other problems, particularly with regard to process variability. For example, it has been shown that high-temperature thermal annealing leads to “shrinkage” of the flowable film when converted into the final silicon oxide film. This shrinkage causes uneven stresses to develop along the fin length, which can lead to undesirable fin bending. As an additional example, high-temperature annealing may also result in insufficient densification of the flowable film when converted into the final silicon oxide film. Thus, insufficient densification may lead to variable etch rates along the resulting STI structure, which can cause uneven STI heights and other variabilities in subsequently-deposited layers of the FinFET. Moreover, apart from the STI structure formation, high-temperature annealing may damage other portions of the FinFET structure. For example, with the introduction of super steep retrograde wells (SSRWs) for the 10 nm regime and smaller, relatively low temperatures are generally maintained throughout the fabrication process to avoid damage to these SSRWs. Accordingly, the prior art, which uses high-temperature thermal annealing with FCVD processes to form high aspect ratio STI structures, is clearly deficient.
Accordingly, it is desirable to provide integrated circuits including FinFET devices with shallow trench isolation that include a dielectric fill that is less susceptible to process variability. In addition, it is desirable to maintain a low “thermal budget” (i.e., a relatively low temperature) throughout the fabrication process to allow for the use of temperature sensitive structures such as SSRWs in small-pitch devices. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.